1. Field of the Invention
This invention relates to non-volatile electrically rewritable or xe2x80x9creprogrammablexe2x80x9d semiconductor memory devices. More particularly, but not exclusively, the invention relates to electrically erasable and programmable read only memory devices.
2. Description of the Related Art
Electrically erasable programmable read only memories (EEPROMS) are arranged to include an array of memory cells, each of which typically has a transistor structure with a floating gate for electrical carrier retention and a control gate as insulatively stacked or xe2x80x9cmultilayeredxe2x80x9d over the floating gate. This memory cell is designed to exhibit a threshold voltage-increased state with electrons injected into the floating gate and a threshold voltage-decreased state with the floating gate electrons released away, which are used for storage of binary digital data bits of a logic xe2x80x9c1xe2x80x9d and a xe2x80x9c0,xe2x80x9d respectively. The memory cell""s data may be read out by first giving a read voltage to the control gate thereof and then detecting or sensing whether this cell turns on (called xe2x80x9con-cellxe2x80x9d) to pull a current thereinto or alternatively is kept turned off (called xe2x80x9coff-cellxe2x80x9d).
Currently available sense amplifiers for memory cell data detection include current-sensing amplifiers. Typically a sense amplifier has a sense node and a reference node. A bit line associated with a selected memory cell is connected to the sense node. Connected to the sense-amp reference node is a reference cell, which permits a reference current for data detection to flow therein. The reference cell is the one that is the same in structure as the EEPROM memory cells. A reference current conducted thereby is typically set at a level that is about one-half of a current of the on-cell. With such an arrangement, the intended data detection is done through comparison of a memory cell current with a current of the reference cell.
EEPROM cells inherently have a variation or deviation in mutual conductance gm value, which can occur due to changes in fabrication process parameters. Observing this state with respect to a memory cell current, experimentation results are as shown in FIG. 18. FIG. 18 is a graph showing a relationship of a control gate voltage Vcg and cell current Icell. Here, there is demonstrated a variation of the cell current Icell occurring upon application of a read voltage Vread to the control gate of a selected memory cell with its threshold voltage Vth. In a way corresponding to a range of from a maximal mutual conductance value gm(max) to a minimal value gm(min), the resultant cell read current would vary within the range of Icell(max) to Icell(min).
As previously stated, the reference current Iref of a reference cell as indicated by dotted line in FIG. 18 is set so that it is about half of the on-cell""s current. If the minimal cell current Icell(min) becomes less than the reference current Iref due to possible variation of gm value, erroneous read can occur. Even where the reference current reduction causes no such read errors, a lengthened time period must be required to execute read due to the fact that an appreciable difference between the cell current and reference current stays less. This makes it impossible to read data at high speeds.
The above problem becomes more serious in the case of multiple-value data storage architectures with the capability for storing multiple bits of information on a single memory cell transistor, also known as xe2x80x9cmultiple-bit-level-per-cellxe2x80x9d or xe2x80x9cmulti-level cell (MLC)xe2x80x9d technologies. For instance, a multi-bit-per-cell storage scheme is known which employs memory cells of the same structure as those used in the case of two-level or xe2x80x9cbinaryxe2x80x9d data storage and which precisely controls threshold value distributions in a way as shown in FIG. 19. The multibit scheme as shown herein is aimed at storage of four-value data with voltage levels xe2x80x9c00,xe2x80x9d xe2x80x9c01,xe2x80x9d xe2x80x9c10,xe2x80x9d and xe2x80x9c11xe2x80x9d in the order that one with a lower threshold voltage precedes others with higher threshold voltages.
Data xe2x80x9c00xe2x80x9d is considered equivalent to the state that a memory cell is at its lowest threshold voltage (called xe2x80x9cVth levelxe2x80x9d from time to time) with electrons released away from the floating gate thereofxe2x80x94for example, define this as an erase state. In order to write or program data xe2x80x9c10xe2x80x9d from this erase state, perform writing of a logic xe2x80x9c1xe2x80x9d of an upper level bit. To write data xe2x80x9c01,xe2x80x9d execute write of a xe2x80x9c1xe2x80x9d of lower bit. To write data xe2x80x9c11,xe2x80x9d first write data xe2x80x9c01xe2x80x9d, and then execute xe2x80x9c1xe2x80x9d-write of upper bit.
Upon execution of the data write or erase operation, a verify-read operation is to be done for forcing each data bit to fall within a prespecified threshold voltage distribution in a similar way to that in the case of binary data. To guarantee the upper and lower limits of such threshold voltage distribution in accordance with respective data xe2x80x9c00,xe2x80x9d xe2x80x9c01xe2x80x9d and xe2x80x9c10xe2x80x9d of FIG. 19, several read voltages (Vvl0, Vvu0), (Vvl1, Vvu1), (Vvl2, Vvu2) should be required in verify-read events.
The resultant threshold voltage distribution of each data thus guaranteed thereby is as follows. For instance, in the case of xe2x80x9c00,xe2x80x9d it falls within a range of from 1.5 to 2.5 volts (V). In the case of xe2x80x9c01,xe2x80x9d it ranges from 3.5 to 4.5V. In the case of xe2x80x9c10,xe2x80x9d it is from 5.5 to 6.5V. For xe2x80x9c11,xe2x80x9d 7.7V or more.
In contrast, in normal or ordinary read operations, read voltages Vread0, Vread1, Vread2 are used, each of which is potentially set between adjacent ones of respective data""s threshold voltage distributions.
To perform such highly precise threshold-voltage distribution control, an increased number of values or levels must be required for the ordinary read and verify-read voltages; in addition, the possible variation/deviation of gm values of memory cells stated previously becomes greater in influenceablity. This can be said because it is required to set up, at fine intervals with increased precision, the reference current of a reference cell in a way pursuant to each ordinary read voltage and verify-read voltage, which would result in a decrease in allowable deviation range of the cell current Icell due to a change in gm as has been discussed in conjunction with FIG. 18.
And, for preclusion of any read errors, an increase in margin should be required in such a way that a marginal space or xe2x80x9cinterspacexe2x80x9d between respective data threshold voltage distributions is set at 1.5V rather than 1V, by way of example. Unfortunately, such margin expansion in this way can result in an extra increase in the upper limit value of a read voltage(s). This upper-limit value increase causes application of a higher voltage to memory cells once at a time whenever a read operation is executed, which in turn causes EEPROMs to decrease in reliability. Another problem encountered with the approach is a decrease in on-chip net areas for layout of memory cells and associative circuitry. This is resulted from an unwanted increase in chip occupation area of xe2x80x9cboosterxe2x80x9d circuits that are operable to generate any required high potential voltages such as read voltages or else. Obviously, the greater the requisite number of high voltages, the more the on-chip area of such boosters.
A non-volatile semiconductor memory device comprises: an array of electrically rewritable or reprogrammable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.